Ph.D. Student, HKUST ECE
Jiangnan Yu
Computer Architecture · ML Systems · Hardware-Software Co-Design
I am a second-year Ph.D. student at The Hong Kong University of Science and Technology (HKUST), advised by Prof. Yuan Xie. My research interests lie at the intersection of computer architecture and machine learning, with a focus on efficient hardware acceleration for sparse computation, in-memory computing, and large language models.
Before joining HKUST, I received my M.S. and B.S. in Microelectronics from Fudan University.
- FocusArchitecture for sparse and LLM workloads
- MethodHardware-software co-design
- AdvisorProf. Yuan Xie
Research Focus
My work explores efficient AI computing systems through architecture innovation and accelerator design.
- Sparse Computing: Accelerators for sparse GEMM with online sparsity prediction.
- In-Memory Computing: Digital stochastic computing in memory and ReRAM-based acceleration for edge AI.
- LLM Acceleration: Multi-chiplet architectures with HBM-PIM for large language model inference.
- Design Automation: NoC generators and event-driven DNN accelerator simulators.
News
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2026
[Paper] DSCIM on Digital Stochastic Computing in Memory was accepted to DATE 2026.
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2025
[Paper] McPAL on Multi-Chiplet HBM-PIM architecture for LLMs was accepted to DAC 2025.
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2025
[Paper] DIRC-RAG on edge RAG acceleration was accepted to ISLPED 2025.
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2024
[Paper] FullSparse on sparse-aware GEMM acceleration was published at CF 2024.
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Jan 2026
Personal website launched.
Education
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Ph.D. in Electronic and Computer Engineering
The Hong Kong University of Science and Technology (HKUST), 2024 - Present
Advisor: Prof. Yuan Xie
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M.S. in Microelectronics
Fudan University (复旦大学), 2021 - 2024
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B.S. in Microelectronics
Fudan University (复旦大学), 2017 - 2021
Selected Publications
*: Equal contributions
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Scalable Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper and Local Attention Reusable Engine for Irregular-Pruned NN
IEEE JETCAS, 2026 Accepted
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DSCIM: Digital Stochastic Computing in Memory Featuring Accurate OR Accumulation for Edge AI Models
DATE, 2026 Accepted
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McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMs
DAC, 2025 Accepted
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DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation
ISLPED, 2025
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FullSparse: A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction
CF, 2024
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TPNoC: An Efficient Topology Reconfigurable NoC Generator
GLSVLSI, 2023
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NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models
ISCAS, 2022
Misc
Hobbies: Running and hiking.